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Senior Digital Design Engineer

Celeno

Celeno

Software Engineering, Design
Graz, Austria
Posted on Saturday, September 24, 2022

 

 

As part of our global expansion program, we have been building our Digital Design Centre in Graz (Austria), and are looking for an experienced (Senior) Digital Design Engineer to join the team. This is a multicultural, diverse, down-to-earth, friendly, agile, yet highly successful team. Join our team and be a part of a world-leading provider of low-power, custom mixed-signal integrated circuits that underpin Mobile, Audio and Gaming devices for some of the world's most recognisable brands.

 

Job Summary

 

  • Designing of optimized digital blocks meeting functional, cost and low power constraints and ensuring spec compliance.
  • Taking over technical leadership for sub-systems or for complete digital system and driving from specification to production ramp.
  • Interface with analog engineers to define the scope of digital and analog functionality for mixed-signal IPs.
  • Developing TCL scripts and design constraints to perform synthesis, DFT insertion and static timing analysis.
  • Supporting DFT strategy and implementation.
  • Verification planning, feature extraction and verification test case development.
  • Interface with P & R for Digital hand-off and post layout verification.
  • Instigating review meetings with Design Engineers.
  • Performing physical silicon device evaluation where necessary.
  • Developing work-around solutions where necessary to overcome device errata including documentation.
  • Supporting RFQ process where necessary.
  • Coaching and mentoring less experienced team members.
  • Other specific tasks deemed reasonable by your Manager some of which will be set during annual performance review.

 

Your Profile

 

 

  • Typically 5 – 8 years’ experience in integrated circuit design
  • Experience working in semiconductors (ideally with focus on mixed signal integrated circuits and low power digital design techniques)
  • Fluent in either (System) Verilog or VHDL RTL coding and ASIC design methodology.
  • Proficiency in developing block and top-level timing constraints for STA and P & R sign off.
  • Proficiency in developing preliminary verification test-bench, writing assertions and formal verification.
  • Very good communication skills in English

 

Renesas Electronics Corporation (TSE: 6723) empowers a safer, smarter and more sustainable future where technology helps make our lives easier. A leading global provider of microcontrollers, Renesas combines our expertise in embedded processing, analog, power and connectivity to deliver complete semiconductor solutions. These Winning Combinations accelerate time to market for automotive, industrial, infrastructure and IoT applications, enabling billions of connected, intelligent devices that enhance the way people work and live. Learn more at renesas.com. Follow us on LinkedIn, Facebook, Twitter, YouTube, and Instagram.

 

Renesas respects all types of diversity and values, and actively works to improve our work environment and foster a corporate culture that accepts and is inclusive of one another. We believe our commitment to diversity and inclusion, and our initiatives are the source of innovative products and services that support our sustainable business growth. For more information, please read through our Diversity & Inclusion Statement.