Job Summary:

• Participate in feasibility studies and sub-block/chip-level architecture definition
• Design and integration of digital sub-blocks at top-level
• Support DFT strategy and implementation
• Work closely with back-end designers to correctly implement digital designs to layout
• Verification planning, verification methodology and test bench development using Verilog/VHDL   
• Static timing analysis (STA), formal verification, logic equivalence checking
• Lab evaluation and debug of digital blocks and full chip function
• Support production test and HW/SW development for evaluation, characterization and testing
• Tape out database and document preparation
• Participate and consult in IC design reviews   
• Attendance at and participation in all relevant project meetings, keeping project manager aware of achievements, issues and potential risks to timescales
• Coach and mentor less experienced engineers
• Demonstrates an ability to learn new tool features and procedures
• Attend training courses or conferences

Your Profile:

• Master’s or Ph.D. in Electrical Engineering or related disciplines

• Preferably some experience in design of analog/digital circuits (0-1 for junior designers, 2-6 years for middle/senior designers)
• Knowledge of Xcelium,(System)Verilog/VHDL/scripting languages
• Full understanding of IC design flow 
• Ability to prioritize work, set goals and meet deadlines
• Self-motivated and take full responsibility for solutions
• Good written, communication and teamwork skills
• (pre-)intermediate English level

Will be a plus:

• Familiarity with Cadence Virtuoso
• Experience with IC technologies, DFT or protocols (UART, I2C, SPI, etc.)
• Knowledge of transistor-level integrated circuits and semiconductor physics
• Understanding of advanced verification methodologies (e.g. UVM, ABV)   
• Familiarity with RTL logic design, design constraints, synthesis, P&R, static timing analysis and formal verification