Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world-leading MCUs, SoCs, analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of the electronics you rely on every day; you may not see our products, but they are all around you.

 

Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what’s next in electronics and the world.

 

 

This role will Integrate , enhance, maintain and deploy foundry Physical Verification decks (DRC/LVS/Extraction)  for internal Analog and Digital design teams and provide support for the same. Including:

 

Conceptualize, specify, develop, deploy, maintain and support new physical verification flows across mature and advanced technology nodes

Foundry deck integration, enhancement and support

Enhancements and bug fixes on EDA tools

Innovation in Physical Verification flows

 

Responsibilities:

• Review, adapt, update, enhance and release foundry DRC/LVS/ Parasitic Extraction/PERC rundecks for Dialog internal customers.
• Provide support to Dialog internal customers (Analog Design teams & Digital P&R design teams) on DRC/LVS and Parasitic extraction
• Coordinate with our internal and external support/development partners on activities
• Interface to EDA tool vendors for Dialog’s tool evaluation and also for requesting enhancements and bug fixes
• Interface with the foundry

 

Experience:

• Degree in Electrical Engineering or Physics
• Good knowledge of CMOS fundamentals with background in electrical engineering or semiconductor physics
• Expert knowledge of tools and programming language for DRC, LVS and Parasitic Extraction (SVRF and TCL) or PVS/Pegasus equivalents
• PERC knowledge a plus
• Knowledge of Perl, Python, TCL a must
• Ideally 10 years’ experience in Physical Verification(Calibre, PVS, Assura ) 
• Experience with Quantus QRC/ StarRC a strong plus
• Familiarity on Cadence custom IC Virtuoso platform, Virtuoso-L and Virtuoso-XL, schematic capture, and layout concepts. 
• Willingness to gain knowledge and familiarity with several CAD tools
• Comfortable, confident working in a fast-paced environment.
• Ability to prioritize work and meet deadlines
• Good interpersonal skills

 

Renesas Electronics America is an equal opportunity and affirmative action employer, committed to celebrating diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by federal, state or local law.