Digital Engineer
Celeno
• Chip integration as Automitive MCU RH850/U2x with 28nm technology.
MCU/IP subsystem verification planning, test infrastructure development, functional verification. Test bench and test case generation using Verilog, System
• Involve to all FE activities (logic design/verification, timing budget) from 1st step as specification design to evaluation:
+ Spec design (Based on checking customer requirement as SRD/PRD)
+ Logic design from each module level to chip level
+ Logic functional verification based on verilog-based-testbench to confirm all required fuctions of chip
+ Logic synthesis and checkers execution/result confirmation
+ Logic timing budget design
• Technical engagement :
+ Use basic tool for standard MCU development flow (e.g: Design Compiler, VCS, Verdi, PrimeTime, Fusion Compiler, Jasper Gold, VC Formal ...)
+ Join GOT (Global One Team) discussion as peer with REL/RDB (Japanese/Chiness)
• Work in suportive/friendly/profressional team. Strong internal coaching/mentoring. Trust is key point of our core building.
SRD: System requirement documentation
PRD: Product requirement documentation