Sr Digital IC Verification Engineer

Responsibilities:

• Develop verification strategy for digital and mixed-signal IC designs
• Verification planning, maintenance, feature extraction, verification tests, coverage and checker development
• Develop efficient, reusable state-of-the-art verification environments and testbench structures following object-oriented programming principles and methodologies including UVM
• Tapeout database and document preparation
• Attendance at and participation in all relevant project meetings, keeping project manager aware of achievements, issues and potential risks to timescales
• Demonstrates an ability to learn new tool features and procedures
• Attend training courses or conferences
• Build up your knowledge and improve your skills using your own research

Your Profile:

• Master’s or Ph.D. in Electrical Engineering, Computer Engineering, Computer Science or related disciplines
• Preferably some experience in analog/digital design, test engineering (0-1 for junior designers, 2-6 years for middle/senior designers)
• Knowledge of electrical properties, digital circuits, behavioral modeling and simulation and Unix
• Ability to debug the RTL Verilog/VHDL design
• Ability to prioritize work, set goals and meet deadlines
• Self-motivated and take full responsibility for solutions
• Good written, communication and teamwork skills
• Pre-Intermediate English

Will be a plus:

• Understanding of IC design workflow
• Knowledge of transistor-level integrated circuits and semiconductor physics
• Experience with protocols (UART, I2C, SPI, JTAG, etc.)
• Programming/scripting (Verilog/VHDL, SystemC/Verilog, TCL, Python, Bash, Perl)
• Understanding of advanced verification methodologies (e.g. UVM, ABV)
• Familiarity with synthesis, P&R, static timing analysis (STA), assertion-based verification and formal verification
• Experience in constrained random verification and metric driven verification
• Experience in simulation and regressions tools e.g. Cadence Incisive, vManager, IMC