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Layout design leader for Mixed Signal LSI



This job is no longer accepting applications

See open jobs at Celeno.
Tokyo, Japan
Posted on Monday, September 4, 2023

Job Type: Permanent - Full Time

Remote Work Available: Yes

Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portolio includes world-leading MCUs, SoCs, analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of the electronics you rely on every day; you may not see our products, but they are all around you.

Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what’s next in electronics and the world.

[Background of Recruitment]

We aim to grow our revenues to over USD 20 billion by 2030.

To achieve this target, our division we will further expand our current product portfolio in IPD, GPU and custom ASIC product lines.

We are looking for engineers who can join our team on this exciting and growth journey and help make a difference to our developments

and team growth.


Lead layout design and verification work of Mixed Signal LSI.

- Chip top layout design and verification.

- Leading of layout design team.

- Layout management with contractors.

- Report preparation and review of layout design.

[Required Skills and Work Experience]


- Analog block layout design and chip top layout design experience

- Layout verification by Candence Virtuso PVS and Mentor Calibre

- Experience of leading design teams

- Layout management with contractors


(One or more of the following)

- Understanding the LSI development process

- Possess knowledge of semiconductor devices

- Digital layout design

- Making rules of physical verification system(modifying current rules and proposing new rules)

[Required Language Skills]

[English]Can have daily conversation (TOEIC 600)

[Japanese]Can have daily conversation

This job is no longer accepting applications

See open jobs at Celeno.