[UCIe] 1 position
    1. Knowledge of UCIe/CXL/PCIe6/CXS.B/AXI
        Eough Experience of specification development
        Enough Experience of logic design and verification using Verilog HDL, System Verilog, UVM
        Enough Experience of Synthesis, STA, SDC, DFT
        Enough Experience of Synopsys IP handling
    2. (if hiring 1 is not possible) 
        Experience of specification development
        Enough Experience of logic design and verification using Verilog HDL, System Verilog, UVM
        Enough Experience of Synthesis, STA, SDC, DFT
        Enough Experience of Synopsys IP handling
[DP] 1 position
    1. Knowledge of DP/HDCP/DSC
        Enough Experience of specification development
        Enough Experience of logic design and verification using Verilog HDL, System Verilog, UVM
        Enough Experience of Synthesis, STA, SDC, DFT
        Enough Experience of Synopsys IP handling
    2. (if hiring 1 is not possible) 
        Experience of specification development
        Enough Experience of logic design and verification using Verilog HDL, System Verilog, UVM
        Enough Experience of Synthesis, STA, SDC, DFT
        Enough Experience of Synopsys IP handling
 [PCIe6/PCIe4/USB3.x/USB2/UFS/CSI/DSI] 4 positions
    Enough Experience of logic design and verification using Verilog HDL, System Verilog, UVM
    Enough Experience of Synthesis, STA, SDC, DFT
    Communication skills with relevant departments or IP vender