Staff Digital Engineer (Radar)
• Design and implementation of SoC, Interface (eg MIPI), Signal conditioning blocks, memory etc
• The candidate will understand and work on all aspects of the VLSI development cycle such as architecture, micro architecture, Synthesis / PD interaction and design convergence and actively work with various core , verification and physical design teams.
• They will perform system architecture, micro-architecture selection, RTL design, simulation, synthesis, timing analysis, lint check, clock domain crossing check, conformal low power check and formal verification in Cadence flow.
• Responsible for IP / sub-system level micro-architecture development and RTL coding.
• Prepare block/sub-system level timing constraints
• Integrate IP/sub-system. Perform basic verification either in IP Verification environment or FPGA.
• Keep track of coverage metrics and bugs encountered and fixed. Implement self-testing directed and random tests. • Support post silicon bring up and debug activities.
• Discuss block and system performance with System Engineers and develop adequate circuit topologies and architectures to fulfil the system requirements.
• Supervise the chip floor-planning and layout, synthesis/clock-tree extractions and verifications.
• Perform/supervise silicon characterization, reliability evaluation and the development of APIs for measurements.
• Prepare and maintain project documentation including general specification, microarchitecture, circuit description, and measurement reports.
Required Education and Experience:
• BE/MTech/MS/PhD with 4-20 years of industrial experience.
• Understanding of micro-architecture to GDS flow.
• Proven track record of Digital ASIC circuit design in CMOS technologies with completed projects from architecture to tape-out and silicon characterization.
• Experience with Cadence tools is a must.
• Experience with 28nm CMOS technologies.
• Good understanding of system specifications and the ability to work with system architects to translate system requirements into circuit requirements at the IC level.
• Familiarity with system and behavioural modelling using MATLAB/Python, System Verilog.
• Hands-on experience in silicon characterization and debug. Knowledge of Python or C (for test and analysis scripting). Knowledge of basic test equipment’s (Oscilloscope, logic analysers etc)
• Must possess good communication and presentation skills and the desire to be part of a dynamic team.
Renesas Electronics Corporation (TSE: 6723) empowers a safer, smarter and more sustainable future where technology helps make our lives easier. A leading global provider of microcontrollers, Renesas combines our expertise in embedded processing, analog, power and connectivity to deliver complete semiconductor solutions. These Winning Combinations accelerate time to market for automotive, industrial, infrastructure and IoT applications, enabling billions of connected, intelligent devices that enhance the way people work and live. Learn more at renesas.com. Follow us on LinkedIn, Facebook, Twitter, YouTube, and Instagram.
Renesas’ mission, To Make Our Lives Easier, is underpinned by our company culture, TAGIE. TAGIE stands for Transparent, Agile, Global, Innovative and Entrepreneurial. Our goal is to embed this unique culture in everything we do to succeed as a company and create trust with our diverse colleagues, customers and stakeholders.
We are committed to creating a diverse culture where everyone is included and feels a sense of belonging. For more information, please read our Diversity & Inclusion Statement.