Renesas RF division, with a focus on delivering smart products for sub-6 5G basestations, Satellite communication, public safety, microwave backhaul, and military/aerospace applications. We are seeking a higher level of integration, where high-performance analog and mixed-signal blocks play a crucial role in the success of the project.

Requirements

• BE 5+ years or M.Tech 3+ years of experience in RF integrated circuit (RFIC) design.
• Hands-on experience in designing RFIC blocks like LNA, Mixer, SW, PA, VGA, etc.
• In-depth knowledge and experience in designing fundamental blocks like amplifiers, matching networks, current mirrors. Knowledge of key RF parameters like Gain, NF, IIP3, OP1dB, ACPR, EVM, etc.
• Excellent understanding of concepts like DC operating point, frequency response, stability, noise, and nonlinearity (IIP3, IP1dB).
• Experience with successful tapeout, lab characterization, and bring-up.
• Proficiency in Keysight ADS, and Cadence Virtuoso suite – Schematic, Maestro, ADEXL, Layout XL, and Spectre/AMS simulations.
• Motivation to work in a multi-disciplinary team for SoC development.
• Good communication skills and effective teamwork.

Preferred

• Experience in power amplifier design is a great plus.
• Knowledge of EM simulations using EMX, Keysight Momentum, HFSS is a big plus.
• Experience in SOI and GaAs technologies is a plus.
• Experience in designing analog mixed-signal blocks like BGR, opamps, and Verilog-based RTL is desired.
• Understanding of post-Si qualification procedures like ESD, HTOL, etc is desired.

Responsibilities

• Work independently to develop innovative and differentiating RFIC blocks and topologies for high-performance ICs.
• Working closely with the chip-lead to derive specifications for RF sub-blocks.
• Do literature survey and propose new innovative architectures to meet the design specifications.
• Work diligently to optimize the design to get the best out of the technology.
• Build simulation test benches and run extensive simulations using Cadence Virtuoso/ADS suite.
• Do RFIC layout and run EM extraction to capture parasitic LRC accurately.
• Document the design procedure and progress in a periodic manner.
• Collaborate and guide other designers and review their work.
• Work with the validation engineers to bring up the chip in the lab and optimize the setting to meet the design specification.

Renesas Electronics Corporation (TSE: 6723) empowers a safer, smarter and more sustainable future where technology helps make our lives easier. A leading global provider of microcontrollers, Renesas combines our expertise in embedded processing, analog, power and connectivity to deliver complete semiconductor solutions. These Winning Combinations accelerate time to market for automotive, industrial, infrastructure and IoT applications, enabling billions of connected, intelligent devices that enhance the way people work and live. Learn more at renesas.com. Follow us on LinkedIn, Facebook, Twitter, YouTube, and Instagram.

Renesas’ mission, To Make Our Lives Easier, is underpinned by our company culture, TAGIE. TAGIE stands for Transparent, Agile, Global, Innovative and Entrepreneurial. Our goal is to embed this unique culture in everything we do to succeed as a company and create trust with our diverse colleagues, customers and stakeholders.

We are committed to creating a diverse culture where everyone is included and feels a sense of belonging. For more information, please read our Diversity & Inclusion Statement.